Since b I B I C, the transistor is saturated. In saturation, the collector current can be calculated by KVL: Therefore, if the transistor is saturated, b I B will be larger than the current actually flowing in the collector-emitter path. If we assume that I B is sufficient to saturate the transistor, then:Ĭollector current won’t increase beyond its saturated value, even if base current increases. Let us assume that this is true and find out if calculations confirm our assumption.įigure 11.19a shows the circuit with V I 3 V. We must prove that V I 3 V is sufficient to saturate the transistor. These two conditions are shown in Figure 11.19. Solution We will analyze the circuit with two input voltages: 3 V (logic HIGH) and 0.5 Assume that b 100, and assume that V BE 0.7 V and V CE 0.2 V in saturation.
With the right choice of input voltages, this circuit acts as a digital inverter.Īnalyze the circuit to show that it acts as an inverter if a logic HIGH is defined as3 V and a logic LOW is defined as 0.5 V. Figure 11.18 shows an NPN bipolar transistor connected in a common-emitter configura.
